The process flow for semiconductor fabrication of integrated circuits (ICs) may include front-end-of-line (FEOL), (MOL), and back-end-of-line (BEOL) processes. The FEOL process may include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The MOL process may include gate contact formation. The BEOL processes may include a series of wafer processing steps for interconnecting the semiconductor devices created during the FEOL and MOL processes. Successful fabrication and qualification of modern semiconductor chip products involves an interplay between the materials and the processes employed. In particular, the gate contact formation during the MOL process is an increasingly challenging part of the process flow, particularly for lithography patterning.
As semiconductor nodes advance (i.e., nodes become smaller and fabrication methodology advances), integrating TSVs (through substrate vias) into MOL layers becomes more difficult. Middle of line layers may include, but are not limited to, MOL contacts or other layers within close proximity to the semiconductor device transistors or other like active devices. The proximity of MOL layers to the device transistors results in narrow process window for successfully integrating the TSVs because MOL layers generally exhibit a reduced thickness. As a result, variability of the die/wafer thickness caused by the TSV integration process becomes more significant to the MOL layers because the TSV process creates vertical connections through the body of the semiconductor device. Moreover, the limited size scaling capability of TSVs further increases their impact on the MOL layers.
One TSV process contributing to die and wafer thickness variability is TSV chemical-mechanical polish (CMP) over-polish. Over-polishing is performed to completely remove all the layers (including films) placed on the wafer by the TSV fill process. In particular, the layers placed on the wafer by the TSV fill process may be formed on an MOL layer of the wafer. Unfortunately, layer removal from the wafer due to over-polishing may further reduce the thickness of the MOL layers, especially for a twenty-nanometer (20 nm) or smaller process.